RISC V/ARM Verification Engineer and Lead

About the job

Hi, We have an opening for RISC V/ARM Verification engineer and Lead role with SV, UVM, Verilog. • Should have hands on verification experience on processor based system, preferably RISC-V/ARM based verification experience. • Understanding of RISC-V/ARM architecture • Must have worked on multiple project on SV-UVM based methodology • Scripting experience is an added advantage • Strong analytical and problem solving skills • Understanding of FPGA flow is an added advantage Please share your resume to Jayalakshmi.r2@ust.com Regards, Jaya

Requirements

• RISC-V
• ARM
• SV-UVM
• Verilog
• Scripting

Preferred Technologies

• RISC-V
• ARM
• SV-UVM
• Verilog
• Scripting

About the company

UST is a company that specializes in technology solutions, focusing on empowering clients to drive their business with innovative technology and solutions. They provide technology services across various industries.